Crossbar circuits (which are also referred to as crossbar switches, cross-point switches, matrix switches, coordinate switching circuits, crossbars, routers, etc.) are a collection of switches or multiplexers which are typically arranged in a matrix configuration. A crossbar switch has multiple input and output lines that form a crossed pattern of interconnecting lines between which a connection may be established by closing a switch located at each intersection.
For example, if the crossbar switch has ‘M’ input lines and ‘N’ output lines, then the crossbar/router has a matrix with M×N cross-points or places where the connections cross. At each cross-point is a crossbar switch, and when the switch is closed, the switch connects one of the input lines to one of the output lines. Typically, concurrent connections in the crossbar switches do not prevent connecting other input lines to other output lines.
Energy-efficient, high-performance crossbar circuits are used for efficient on-chip communication. On-chip communication limits processor performance and power, and is becoming increasingly crucial because of process scaling and core-count increases, where core-count are count of processing elements (e.g., cores, caches, memory controllers, etc.). Crossbars enable data exchange among a set of ports having input and output lines. Crossbars may directly connect processing elements to each other in a full crossbar. Or, crossbars may be networked to relay data between cores using a series of router switches.
For high throughput, many crossbar switches rely on wide data busses. Here, data bus width is indicated by ‘d’ (i.e., number of bits), and crossbar radix is indicated by ‘p’ (i.e., number of ports). As ‘d’ increases, the physical dimension of the entire crossbar grows, which increases the interconnection lengths for each data bit (i.e., propagation delay increases). As ‘p’ increases, data must be broadcast to more distant locations in the crossbar (i.e., more drivers are needed and thus more power is consumed). For lower latency in a Network-on-Chip (NoC), crossbar switches should accommodate higher radices (i.e., higher values for ‘p’). However, traditional crossbar design techniques and associated floorplans exhibit limited scalability in terms of ‘d’ and ‘p.’ For example, propagation delay and power consumption for traditional crossbars scale quadratically with respect to both data bus width and the number of ports. This leads to performance and power degradation for a NoC.